Methods of generating a pixel clock signal from a transmission clock signal and related data transmission methods for multimedia sources

ABSTRACT

Methods of generating a pixel clock signal for a multimedia source are provided in which a transmission clock signal having a first frequency is generated from a reference clock signal that has a second frequency. The generated transmission clock signal is multiplied by a multiple to generate the pixel clock signal. The pixel clock signal has a third frequency that is the product of the second frequency and the multiple,

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §120 as a divisionalapplication of U.S. patent application Ser. No. 12/575,523, filed Oct.8, 2009, which in turn claims priority under 35 U.S.C. §119 to KoreanPatent Application No. 2008-101611, filed on Oct. 16, 2008, in theKorean Intellectual Property Office. The entire contents of each of theabove applications are incorporated by reference as if set forth fullyherein.

BACKGROUND

The present invention relates to methods of generating clock signalsand, more particularly, to methods of generating clock signals for amultimedia source and related data transmission methods.

A typical multimedia system includes a multimedia source that provides amultimedia signal such as, for example, a DVD player or a set-top box,and a multimedia output/display device such as, for example, atelevision, that outputs a multimedia signal that is provided from themultimedia source.

An interface is used to transmit and receive data between the multimediasource and the multimedia output device. Two interface protocols thathave been recently adopted are the High Definition Multimedia Interface(HDMI) and the Digital Video Interface (DVI). A cable converter may beused to convert between DVI and HDMI, thereby allowing, for example, aconnection between a DVI multimedia source and an HDMI multimedia outputdevice.

A Transition Minimized Differential Signaling (TMDS) method may be usedto transmit data between a multimedia source and a multimedia outputdevice when HDMI or DVI are used. The TMDS method includes a video dataperiod, a data island period, and a control period. Active video data istransmitted during the video data period. Packets of audio informationand supplementary data are transmitted during the data island period.Preamble data is transmitted during the control period.

SUMMARY

Pursuant to embodiments of the present invention, methods oftransmitting data from a multimedia source are provided in which atransmission clock signal that has a first frequency is generated bymultiplying a reference clock signal that has a second frequency that isdifferent than the first frequency. The generated transmission clocksignal is multiplied to generate a pixel clock signal that has a thirdfrequency that is different than the first and second frequencies. Thetransmission clock signal is output from the multimedia source at thetime serial data of the multimedia source is transmitted.

In some embodiments of these methods, the transmission clock signal maybe generated by multiplying a reference clock signal using aphase-locked loop or a delay-locked loop to generate an intermediateclock signal having a fourth frequency and then dividing theintermediate clock signal having the fourth frequency by five togenerate the transmission clock signal. The method may also includelatching parallel data of the multimedia source to generate the serialdata at a rising or a falling point of the intermediate clock signal. Insome embodiments, the third frequency of the pixel clock signal may be1, ⅘, ⅔ or ½ the first frequency of the transmission clock signal. Insome embodiments, the duty error of the pixel clock signal may becorrectable.

In one specific embodiment, the third frequency of the pixel clocksignal may be ⅘ the first frequency of the transmission clock signal,and this pixel clock signal may be generated by passing the transmissionclock signal through a divider that divides by a factor of five and thenpassing the output of the divider through a first frequency doubler andthen passing the output of the first frequency doubler through a secondfrequency doubler. In another specific embodiment, the third frequencyof the pixel clock signal may be ⅔ the first frequency of thetransmission clock signal, and this pixel clock signal may be generatedby passing the transmission clock signal through a divider the dividesby a factor of three and then passing the output of the divider througha frequency doubler. In yet another specific embodiment, the thirdfrequency of the pixel clock signal may be ½ the first frequency of thetransmission clock signal, and this pixel clock signal may be generatedby passing the transmission clock signal through a divider that dividesby a factor of two. In some embodiments, the multimedia source maygenerate a plurality of pixel clock signals, and one of this pluralityof pixel clock signals may be selected for use by the multimedia sourcebased on a color depth of the data of the multimedia source.

Pursuant to further embodiments of the present invention, methods oftransmitting data of a multimedia source are provided in which areference clock signal having a first frequency is multiplied togenerate a transmission clock signal having a second frequency. Thegenerated transmission clock signal is multiplied to generate a pixelclock signal having a third frequency. Parallel data is then convertedinto serial data in synchronization with the generated pixel clocksignal. The serial data and the transmission clock signal are thentransmitted to an external device.

Pursuant to still further embodiments of the present invention, methodsof generating a pixel clock signal for a multimedia source are providedin which a transmission clock signal having a first frequency isgenerated from a reference clock signal that has a second frequency thatis different than the first frequency. The generated transmission clocksignal is multiplied by a multiple to generate the pixel clock signalthat has a third frequency that is the product of the second frequencyand the multiple.

In some embodiments, the transmission clock signal may be multiplied bythe multiple to generate the pixel clock signal by passing thetransmission clock signal through at least two multiplier and/or dividercircuits to generate the pixel clock signal. Moreover, the transmissionclock signal may be passed through a first multiplication path thatincludes at least one multiplier and/or divider circuit to generate afirst potential pixel clock signal and passed through a secondmultiplication path that includes at least one multiplier and/or dividercircuit to generate a second potential pixel clock signal. In suchembodiments, the pixel clock signal may be generated by selecting one ofthe first potential pixel clock signal and the second potential pixelclock signal as the pixel clock signal based on a color depth of videodata that is to be transmitted by the multimedia source.

In some embodiments, a single phase locked loop or delay locked loop isused to generate the pixel clock signal from the reference clock signal.Moreover, generating the transmission clock signal having the firstfrequency from the reference clock signal that has the second frequencymay involve multiplying the reference clock signal using amultiplication unit to generate an intermediate clock signal and thendividing the intermediate clock signal using a divider to generate thetransmission clock signal. In such embodiments, the single phase lockedloop or delay locked loop may be part of the multiplication unit.

In another exemplary embodiment, a method of transmitting data of amultimedia source may comprise: multiplying a frequency of a referenceclock to generate a transmission clock; dividing or multiplying afrequency of the generated transmission clock to generate a pixel clock;converting parallel data in synchronization of the pixel clock intoserial data; and transmitting the serial data and the transmission clockto an external source.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate example embodimentsof the present invention and, together with the description, serve toexplain principles of the present invention. In the drawings:

FIG. 1 is a block diagram of a multimedia source according to certainembodiments of the present invention.

FIG. 2 is a block diagram of a first embodiment of the clock generatorof FIG. 1.

FIG. 3 is a block diagram of a second embodiment of the clock generatorof FIG. 1.

FIG. 4 is a block diagram of a third embodiment of the clock generatorof FIG. 1.

FIG. 5 is a block diagram of a fourth embodiment of the clock generatorof FIG. 1.

FIG. 6 is a flow chart illustrating a method of transmitting multimediadata according to embodiments of the present invention.

FIG. 7 is a block diagram of a multimedia system having a multimediasource according to certain embodiments of the present invention.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention, however, may be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thicknesses of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout the accompanyingfigures.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(i.e., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis disclosure and the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

Multimedia sources according to embodiments of the present invention maygenerate a transmission clock signal and may then generate a pixel clocksignal by dividing or multiplying the generated transmission clocksignal. Accordingly, the multimedia sources according to someembodiments of the present invention may use fewer phase-locked loops(PLL) for clock signal generation purposes as compared to conventionalmultimedia sources.

FIG. 1 depicts a multimedia source 100 according to certain embodimentsof the present invention. As shown in FIG. 1, the multimedia source 100includes a video processor 120, a transmitter 140, and a clock generator160. The clock generator 160 includes a pixel clock generator 165 thatis configured to generate a pixel clock signal Pixel CLK from atransmission clock signal TMDS CLK. The multimedia source 100 depictedin FIG. 1 may comprise, for example, a television, a DVD player or aset-top box.

The transmitter 140 that is depicted in FIG. 1 is an HDMI transmitter.However, it will be appreciated that other types of transmitters may beused. Thus, for example, any transmitter may be used that has an outputtransmission clock signal TMDS CLK that has a frequency that is greaterthan the frequency of the generated pixel clock signal Pixel CLK.

The video processor 120 controls operations for transmitting image datato an external device. The video processor 120 outputs parallel data insynchronization with the pixel clock signal Pixel CLK. In other words,the frequencies of the pixel clock signal and the parallel data areidentical. The parallel data may include R-pixel data, G-pixel data andB-pixel data (i.e., red-green-blue pixel data). The video processor 100may compress the image data that is to be transmitted using, forexample, Moving Picture Experts Group (MEPG), Joint Photographic ExpertsGroup (JPEG), or other data compression methods.

The pixel clock signal Pixel CLK is input from the pixel clock generator165 of the clock generator 160. The pixel clock signal Pixel CLK is usedas a digital clock of a link logic (not shown) or of the video processor120.

The transmitter 140 receives the parallel data and the pixel clocksignal Pixel CLK that are output from the video processor 120, andfurther receives the transmission clock signal TMDS CLK and anotherclock signal 5X TMDS CLK that has a frequency which is five times thefrequency transmission clock signal TMDS CLK from the clock generator160. The transmitter 140 latches the parallel data at a rising or apolling point of the 5X TMDS CLK signal. The transmitter 140 outputsserial data TMDS DATA and the transmission clock signal TMDS CLK. Thefrequency of the transmission clock signal TMDS CLK is ten times thefrequency of the serial data TMDS DATA. Although not shown, thetransmission clock signal TMDS CLK and the serial data TMDS DATA may betransmitted as differential signals.

The clock generator 160 includes the transmission clock generator 161and the pixel clock generator 165. The transmission clock generator 161may generate the transmission clock signal TMDS CLK by multiplying areference clock signal Ref CLK. The pixel clock generator 165 maygenerates the pixel clock signal Pixel CLK by multiplying or dividingthe transmission clock signal TMDS CLK that is generated by thetransmission clock generator 161 and input to the pixel clock generator165.

In a typical multimedia source, two or three PLLs may be used to supportuse of deep colors. For example, one PLL may be used to generate a pixelclock signal, one PLL may be used to generate a transmission clocksignal, and another PLL may be used to resolve jitter that may occurbetween the pixel clock signal and the transmission clock signal.However, the number of PLLs may impact both the size and/or the powerrequirements of the multimedia source. Also signal interference mayoccur between the PLLs.

Pursuant to embodiments of the present invention, multimedia sources areprovided that may use reduced numbers of PLLs. For example, themultimedia source 100 may use a single PLL to support the use of deepcolor. The multimedia source 100 initially generates the transmissionclock signal, and then generates the pixel clock signal from thetransmission clock signal. The pixel clock signal may be generated bymultiplying the transmission clock signal by one or more multipliers(note that herein the term “multiplying encompasses both multiplicationand division operations, as a division operation may be viewed as amultiplication operation with a multiplier having a value that is lessthan 1). As such, the multimedia source 100 may include a single PLLthat is used to generate the transmission clock signal TMDS CLK.

FIG. 2 illustrates a first embodiment of the clock generator 160 ofFIG. 1. In FIG. 2, the clock generator 160 includes a transmission clockgenerator 161 and a pixel clock generator 165.

The transmission clock generator 161 includes a clock multiplicationunit CMU 162 and a divider 163. The clock multiplication unit 162receives the reference clock signal Ref CLK which it uses to generatethe clock signal 5X TMDS CLK that has a frequency that is five times thefrequency of the transmission clock signal TMDS CLK. The clock signal 5XTMDS CLK is used to convert parallel data into serial transmission data.The divider 163 divides the frequency of the clock signal 5X TMDS CLK byfive to generate the transmission clock signal TMDS CLK. The referenceclock signal Ref CLK may be obtained, for example, from a highly precisecrystal oscillator.

The clock multiplication unit 162 includes a PLL or a delay locked loopDLL. A clock multiplication unit 162 that includes a PLL uses a phasefrequency detector to detect a phase/frequency difference between thedivider clocks. The divider clocks correspond to the clock that dividesfrequencies of input clock and output clock by N. The clockmultiplication unit controls the frequency of the output clock based onthe detected phase/frequency difference between the divider clocks. Aclock multiplication unit that uses a DLL uses the phase frequencydetector to detect the phase/frequency difference between the inputclock and the output clock, and controls delay between a plurality ofdelay cells included in delay lines, based on the detected result.

The pixel clock generator 165 multiplies the transmission clock signalTMDS CLK to generate a plurality of pixel clock signals, and selects oneof the generated pixel clock signals based on the color depth. Herein,the “color depth” refers to the number of bits that are used to storecolor information. For example, if a color depth of a G-pixel is 10bits, 10 bits are used to store color information of the G-pixel.

In the particular embodiment of the clock generator 160 depicted in FIG.2, the pixel clock generator 165 includes dividers 171, 174, 176,frequency doublers 172, 173, 175, and a multiplexer 177. The dividers171, 174, 176 and the frequency doublers 172, 173, 175 are each“multipliers” as they take an input clock signal having a firstfrequency and output a clock signal having a second frequency that is aninteger or non-integer multiple of the first frequency. In particular,the dividers 171, 174 and 176 generate clock signals having a frequencyequal to the frequency of an input clock signal that is divided by apredetermined number (here 5, 3 and 2, respectively for dividers 171,174 and 176). The frequency doublers 172, 173, and 175 generate clocksignals having a frequency which is twice the frequency of an inputclock signal. The dividers 171, 174 and 175 and the frequency doublers172, 173 and 175 do not use PLLs or DLLs.

The color depths are subject to change according to the ratio of thefrequencies of the transmission clock signal TMDS CLK and the pixelclock signal Pixel CLK. For example, when the color depth is 8-bits, theratio is 1:1, when the color depth is 10-bits, the ratio is 1.25:1, whenthe color depth is 12-bits, the ratio is 1.5:1, and when the color depthis 16-bits, the ratio is 2:1. Accordingly, when the transmission clocksignal TMDS CLK is multiplied by 1, ⅘, ⅔ and ½, respectively, pixelclock signals Pixel CLK of 8, 10, 12, and 16 bits are obtained.

A clock signal having a frequency which is ⅘ the frequency of thetransmission clock signal TMDS CLK may be generated by passing the clocksignal TMDS CLK through the divider 171 which divides the frequency ofthe clock signal TMDS CLK by five. The clock signal at the output of thedivider 171 is passed through the frequency doublers 172 and 173, eachof which multiply the clock frequency by two. A clock signal having afrequency which is ⅔ the frequency of the transmission clock signal TMDSCLK may be generated by passing the clock signal TMDS CLK through thedivider 174 which divides the frequency of the clock signal TMDS CLK bythree, and then passing the output of divider 174 through the frequencydoubler 175 which multiplies the clock frequency by two. A clock signalhaving a frequency which is ½ the frequency of the transmission clocksignal TMDS CLK may be generated by passing the clock signal TMDS CLKthrough the divider 176 which multiplies the clock frequency by two. Themultiplexer 177 selects one of the transmission clock signal TMDS CLK,the clock signal having a frequency that is ⅘ the frequency of thetransmission clock signal, the clock signal having a frequency that is ⅔the frequency of the transmission clock signal, and the clock signalhaving a frequency that is ½ the frequency of the transmission clocksignal, according to the color depth, and then outputs one of theseclock signals as the pixel clock signal Pixel CLK.

The frequency doublers 172, 173 and 175 may include duty cycle correctorcircuits (DCC). These DCCs correct a duty cycle of the clock signal to apredetermined value, and maintain the duty cycle of the clock signal atthis predetermined value. The “duty” of a clock signal refers to theratio between the period when the clock signal is at a logical highstate and the period when the clock signal is at a logical low state.For example, if the periods of the logical high state and the logicallow state are identical, the duty is 50%.

The clock generator 160 of FIG. 2 selects a pixel clock signal based onthe color depth of the multimedia source. However, the clock generatorsaccording to embodiments of the present invention are not limited toselecting the pixel clock signal.

FIG. 3 illustrates a second embodiment of the clock generator 160 ofFIG. 1. As shown in FIG. 3, the clock generator 160 includes thetransmission clock generator 161 that is discussed above with referenceto FIG. 2 and a pixel clock generator 166. The pixel clock generator 166includes a divider 181 and multipliers 182 and 183. The divider 181divides the transmission clock signal TMDS CLK by five to provide aclock signal having a frequency that is one fifth the frequency of thetransmission clock signal TMDS CLK. The multipliers 182 and 183 eachmultiply the frequency of the signals input thereto by two. Thus,together, the divider 181 and the multipliers 182 and 183 may be used toprovide a pixel clock signal having a frequency that is ⅘ the frequencyof the transmission clock signal TMDS CLK.

FIG. 4 illustrates a third embodiment of the clock generator 160 ofFIG. 1. As shown in FIG. 4, the clock generator 160 includes thetransmission clock generator 161 and a pixel clock generator 167. Thepixel clock generator 167 includes a divider 184 and a multiplier 185.The divider 184 divides the transmission clock signal TMDS CLK by threeto provide a clock signal having a frequency that is one third thefrequency of the transmission clock signal TMDS CLK. The multiplier 185multiplies the clock signal input thereto by two. Together, the divider184 and the multiplier 185 may be used to provide a pixel clock signalhaving a frequency that is ⅔ the frequency of the transmission clocksignal TMDS CLK.

FIG. 5 illustrates a fourth embodiment of the clock generator 160 ofFIG. 1. As shown in FIG. 5, the clock generator 160 includes thetransmission clock generator 161 and a pixel clock generator 168. Thepixel clock generator 168 includes a divider 186 that divides the inputclock signal TMDS CLK by two to provide a pixel clock signal having afrequency that is ½ the frequency of the transmission clock signal TMDSCLK.

FIG. 6 is a flow chart illustrating a method of transmitting multimediadata according to embodiments of the present invention. Referring toFIG. 1 and FIG. 6, the data transmitting method of this embodiment mayproceed as follows.

When transmitting data of multimedia source, a clock generator such asthe clock generator 160 of FIG. 1 generates a transmission clock signalTLDS CLK from a reference clock signal Ref CLK (S110). The transmissionclock signal TMDS CLK may be generated using a PLL to provide a preciseclock signal.

The clock generator 160 uses the transmission clock signal TMDS CLK togenerate a pixel clock signal Pixel CLK (S120). The pixel clock signalPixel CLK may be generated by multiplying or dividing the transmissionclock signal TMDS CLK. The multiplication and division operations thatare performed may be selected based on the color depth of the multimediasource. For example, when the color depth of the multimedia source is 10bits, a pixel clock signal Pixel CLK that has a frequency that is ⅘ thefrequency of the transmission clock signal TMDS CLK may be used as thepixel clock signal Pixel CLK.

The transmitter 140 receives parallel data based on color depth, andlatches data at a rising point and a falling point of the clock signal5X TMDS CLK to generate serial transmission data TMDS DATA. Thetransmitter 140 outputs the transmission data TMDS DATA and thetransmission clock TMDS CLK thus generated (S130).

FIG. 7 illustrates a multimedia system 10 having a multimedia sourceaccording to certain embodiments of the present invention. As shown inFIG. 7, the multimedia system 10 includes a multimedia source 12 and amultimedia output device 14 (e.g., a display device). The multimediasource 12 may be configured identically to the multimedia source 100, ofFIG. 1. The multimedia source 12 includes a transmitter 13 that switchesparallel image data into high-speed serial data.

The multimedia output device 14 includes a receiver 15 that isconfigured to receive high-speed serial data transmitted from themultimedia source 12. The multimedia output device 14 includes a device(not shown) which converts input serial image data and outputs theconverted data. The multimedia output device 14 may be, for example, atelevision set, a PDA, a cellular telephone, or a navigation system.

The multimedia source 12 and the multimedia output device 14 may beconnected by a TMDS link that may support high-speed data transmission.This TMDS link may have the characteristics described below.

Video data (e.g., each 8-bit digital video data word) and otherinformation is encoded (e.g., into a 10-bit encoded word) prior totransmission. The encoder generates “out-of-band” words in response tocontrol signals or synchronizing signals, and generates “in-band” wordsin response to video data. Each “in-band” word is an encoded wordgenerated as a result of encoding one input video data word. All thewords except for “in-band” words transmitted via the link are“out-of-band” words. The encoding of the video data is performed so thatthe transition of the “in-band” words may be minimized. In other words,the sequence of the “in-band” words has a reduced or minimum transitionnumber. The encoding of video data is performed so that the “in-band”words are DC balanced. Encoding keeps the voltage wave which transfers asequence of “in-band” words from going out of bound from between areference voltage and a predetermined threshold voltage. In particular,the 10^(th) bit of each “in-band” word indicates whether 8-bits out of 9other bits of the “in-band” word are inverted, and corrects unbalancebetween the previously encoded stream of data bits to the running countsof 1s and 0s.

The encoded video data and video clock signal are transferred asdifferential signals over pairs of conductors. In some embodiments,three pairs of conductors may be used to transmit the encoded videosignal, and a fourth pair of conductors may be used to transmit a videoclock signal. These signals may be transmitted in only one directionfrom the transmitter (e.g., a desk top, a portable computer, or otherhosts) to the receiver (e.g., a monitor or other display deviceelement).

The multimedia source 12 and the multimedia output device 14 may both beconnected to a High Definition Multimedia Interface (HDMI). HDMIinterfaces integrate video signal and audio signal into one digitalinterface, and are commonly used in audio/visual appliances such as, forexample, DVD players, HDTVs, and set-top boxes. The High BandwidthDigital Content Protection (HDCP) copy protection is adopted as thebasis of HDMI. DVI is the key technology, and HDCP is a copyrightprotected invention which is a base band made by Intel Corporation. TheHDCP requires a mutual verification between the devices as does theDTCP. The HDMI supports a standard to multi-channel audio signal, aswell as standard, extended and HD video. The HDMI is capable oftransmitting a non-compressed digital video signal of 5 gigabits persecond as a single terminal, from a source device 12 to a display device14.

Although the present invention has been described in connection withcertain embodiments of the present invention that are illustrated in theaccompanying drawings, the present invention is not limited to theembodiments pictured herein. Persons with skill in the art willrecognize that embodiments of the present invention may be applied toother types of devices. The above-disclosed subject matter is to beconsidered illustrative, and not restrictive, and the appended claimsare intended to cover all such modifications, enhancements, and otherembodiments, which fall within the true spirit and scope of the presentinvention. Thus, to the maximum extent allowed by law, the scope of thepresent invention is to be determined by the broadest permissibleinterpretation of the following claims and their equivalents, and shallnot be restricted or limited by the foregoing detailed description.

What is claimed is:
 1. A method of generating a pixel clock signal of amultimedia source, the method comprising: multiplying a frequency of areference clock signal to generate a transmission clock signal;outputting the transmission clock signal at the time data of themultimedia source is transmitted; dividing a frequency of the generatedtransmission clock signal; and multiplying a frequency of the dividedtransmission clock signal to generate the pixel clock signal of themultimedia source.
 2. The method of claim 1, wherein a clockmultiplication unit is used to multiply the frequency of the referenceclock signal by a predetermined amount to generate the transmissionclock signal.
 3. The method of claim 2, further comprising generatingthe reference clock signal using a phase-locked loop or a delay-lockedloop.
 4. The method of claim 2, further comprising dividing a frequencyof the clock signal that is output from the clock multiplication unit togenerate the transmission clock signal.
 5. A method of transmitting dataof a multimedia source comprising: multiplying a frequency of areference clock signal to generate a transmission clock signal; dividinga frequency of the generated transmission clock signal; multiplying afrequency of the divided transmission clock signal to generate a pixelclock signal; converting parallel data in synchronization with the pixelclock signal into serial data; and transmitting the serial data and thetransmission clock signal to an external source.
 6. A multimedia system,comprising: a multimedia source that is configured to convert paralleldata into serial data and to generate a transmission clock signal; and amultimedia output device that is configured to receive the serial datafrom the multimedia source in synchronization with the transmissionclock signal, wherein the multimedia source comprises, a clock generatorthat is configured to generate the transmission clock signal from areference clock signal and to generate a pixel clock signal by bothdividing and multiplying a frequency of the transmission clock signal; avideo processor that is configured to generate the parallel data insynchronization with the pixel clock signal; and a transmitter that isconfigured to output the serial data in synchronization with thetransmission clock signal.
 7. The multimedia system of claim 6, whereinthe multimedia source further comprises a phase locked loop that isconfigured to generate the reference clock signal.
 8. The multimediasystem of claim 6, wherein the clock generator that is configured togenerate the pixel clock signal by both dividing and multiplying thefrequency of the transmission clock signal comprises a clock generatorthat is configured to generate the pixel clock signal by first dividinga frequency of the transmission clock signal and by then multiplying afrequency of the divided transmission clock signal.
 9. The method ofclaim 6, wherein the frequency of the pixel clock signal is ⅘ thefrequency of the transmission clock signal.